module EX(
    input [7:0] Reg0_data,// from Regfile/memory
    input [7:0] Reg1_data,// from Regfile/immediate
    input [7:0] Dst_data,
    
    input [2:0] opcode,// to ALU and Branch unit
    input [7:0] offset,// TO branch unit
    input [7:0] PC, //from Original PC

    output reg [7:0] Reasult_data// to Regfile/memory
    
);

    localparam [2:0] 
                add=3'b000,
                addi=3'b001,
                sub=3'b010,
                subi=3'b011,
                move=3'b100,
                movei=3'b101,
                beq=3'b110,
                blt=3'b111;
                    
    always @(opcode or Reg0_data or Reg0_data) begin
        case (opcode)
        
            add,addi: Reasult_data=Reg0_data+Reg1_data;
            sub,subi: Reasult_data=0;
            move,movei: Reasult_data= 
            default : result=0;
        
        endcase                
    end

 
endmodule

